Electronic component and manufacturing method thereof

ABSTRACT

The electronic component includes a semiconductor substrate, a first doped region, a second doped region, a gate structure, a dielectric layer and a conductive portion. The semiconductor substrate has an upper surface. first doped region embedded in the semiconductor substrate. The second doped region is embedded in the semiconductor substrate. The gate structure is formed on the upper surface. The dielectric layer is formed above the upper surface and located between the first doped region and the second doped region. The conductive portion is formed on the dielectric layer.

This application claims the benefit of U.S. Provisional application Ser.No. 62/204,156, filed Aug. 12, 2015, the disclosure of which isincorporated by reference herein in its entirety.

FIELD OF THE INVENTION

The invention relates to an electronic component and a manufacturingmethod thereof, and more particularly to an electronic component havinga conductive portion and a manufacturing method thereof.

BACKGROUND OF THE INVENTION

In conventional electronic component, a shallow trench isolations (STI)is embedded in a substrate and located a gate structure and a drain forincreasing the endurance to voltage. However, the embedded STI increasesthe length between the gate structure and the drain, and it causes theimpedance between the gate structure and the drain to increase.

Therefore, it is important how to reduce the impedance between the gatestructure and the drain.

SUMMARY OF THE INVENTION

In one embodiment of the invention, an electronic component is provided.The electronic component includes a semiconductor substrate, a firstdoped region, a second doped region, a gate structure, a dielectriclayer and a conductive portion. The semiconductor substrate has an uppersurface. The first doped region is embedded in the semiconductorsubstrate. The second doped region is embedded in the semiconductorsubstrate. The gate structure is formed on the upper surface. Thedielectric layer is formed above the upper surface and located betweenthe first doped region and the second doped region. The conductiveportion is formed on the dielectric layer.

In another embodiment of the invention, an electronic component isprovided. The electronic component includes a semiconductor substrate, afirst doped region, a second doped region and a conductive portion. Thesemiconductor substrate has an upper surface. The first doped region isembedded in the semiconductor substrate. The second doped region isembedded in the semiconductor substrate. The conductive portion isformed on the dielectric layer and located between the first dopedregion and the second doped region but not formed on any doped regionbetween the first doped region and the second doped region.

In another embodiment of the invention, a manufacturing method of anelectronic component is provided. The manufacturing method includes thefollowing steps. A dielectric layer material is formed above an uppersurface of a semiconductor substrate, wherein the dielectric layermaterial covers a gate structure formed on the upper surface; a portionof the dielectric layer material is removed, wherein another portion ofthe dielectric layer material is retained to form a dielectric layer,and the dielectric layer formed above the upper surface is locatedbetween the first doped region and the second doped region; a firstdoped region and a second doped region embedded in the semiconductorsubstrate are formed; and a conductive portion on the dielectric layeris formed.

In another embodiment of the invention, a manufacturing method of anelectronic component is provided. The manufacturing method includes thefollowing steps. A dielectric layer material is formed above an uppersurface of a semiconductor substrate; wherein the dielectric layermaterial covers a gate structure formed on the upper surface; a portionof the dielectric layer material is removed, wherein another portion ofthe dielectric layer material is retained to form a dielectric layer;and the dielectric layer formed above the upper surface is locatedbetween the first doped region and the second doped region; a firstdoped region and a second doped region embedded in the semiconductorsubstrate are formed; and a conductive portion is formed on thedielectric layer, wherein the conductive portion is located between thefirst doped region and the second doped region but not formed on anydoped region between the first doped region and the second doped region.

Numerous objects, features and advantages of the invention will bereadily apparent upon a reading of the following detailed description ofembodiments of the invention when taken in conjunction with theaccompanying drawings. However, the drawings employed herein are for thepurpose of descriptions and should not be regarded as limiting.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the invention will become morereadily apparent to those ordinarily skilled in the art after reviewingthe following detailed description and accompanying drawings, in which:

FIG. 1 illustrates a diagram of an electronic component according to anembodiment of the invention;

FIG. 2 illustrates a top view of the electronic component of FIG. 1;

FIG. 3 illustrates a top view of the electronic component of FIG. 1according another embodiment; and

FIGS. 4A to 4F illustrate manufacturing processes of the electroniccomponent of FIG. 1.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 illustrates a diagram of an electronic component 100 according toan embodiment of the invention. The electronic component 100 is, forexample, a metal-oxide-semiconductor (MOS) structure.

The electronic component 100 includes a semiconductor substrate 110, afirst isolation portion 112, a second isolation portion 114, a firstdoped region 122, a second doped region 124, a gate structure 130, astop layer 140, a dielectric layer 150, a layer structure 160, aplurality of first contacts 172 and 174 and a least one conductiveportion 180.

The semiconductor substrate 110 is, for example, silicon wafer. Thesemiconductor substrate 110 has an upper surface 110 u. The firstisolation portion 112 and the second isolation portion 114 are embeddedin the semiconductor substrate 110 and located below the upper surface110 u. In an embodiment, the first isolation portion 112 and the secondisolation portion 114 are shallow trench isolations (STI), for example.

The first doped region 122 and the second doped region 124 are embeddedin the semiconductor substrate 110 and located below the upper surface110 u. The first doped region 122 and the second doped region 124 arelocated between the first isolation portion 112 and the second isolationportion 114. In an embodiment, the first doped region 122 and the seconddoped region 124 may be heavily doped regions, such as N-type heavilydoped regions. Furthermore, the first doped region 122 and the seconddoped region 124 may be salicides. In an embodiment, one of the firstdoped region 122 and the second doped region 124 may be a source, andanother of the first doped region 122 and the second doped region 124may be a drain.

The gate structure 130 is formed on the upper surface 110 u. The gatestructure 130 includes a dielectric layer 130′, a gate 134 and a spacer135. In an embodiment, the dielectric layer 130′ includes a first oxidelayer, a nitride layer and a second oxide layer, wherein the nitridelayer is formed between the first oxide layer and the second oxidelayer. The first oxide layer, the nitride layer and second oxide layermay form an ONO structure. In another embodiment, the dielectric layer130′ may be a single-layered structure. The gate 134 is formed on thedielectric layer 130. The spacer 135 is formed on a side all 130 w ofthe ONO structure 130′ and a side all 134 w of the gate 134. In anotherembodiment, the gate structure 130 may have other structure differentfrom that of the gate structure 130 of FIG. 1.

The stop layer 140 covers the upper surface 110 u of the semiconductorsubstrate 110, the gate structure 130 and the dielectric layer 150. Thestop layer 140 may be made of a material such as nitride oxide.

The entire dielectric layer 150 is formed above the upper surface 110 uof the semiconductor substrate 110 and located between the upper surface110 u and the stop layer 140. As a result, the dielectric layer 150 doesnot increase the length of the current path between the gate structure130 and the second doped region 124 or may reduce the length of thecurrent path between the gate structure 130 and the second doped region124, and accordingly the impedance between the gate structure 130 andthe second doped region 124 may be reduced.

The dielectric layer 150 is located between the first doped region 122and the second doped region 124. As shown in FIG. 1, the dielectriclayer 150 does not be formed on any doped region between the first dopedregion 122 and the second doped region 124. The dielectric layer 150 maybe a blockage film that defines the regions of the first doped region122 and the second doped region 124. In an embodiment, the dielectriclayer 150 may be made of SiO, SiON, SiN or any insulator.

The dielectric layer 150 covers at least one portion of an upper surface130 u of the gate structure 130 and a lateral surface of the gatestructure 130. For example, the dielectric layer 150 covers a portion ofthe lateral surface 135 w of the spacer 135, and another portion of thelateral surface 135 w of the spacer 135 is covered IT the stop layer140. In another embodiment, the dielectric layer 150 may not cover theupper surface 130 u of the gate structure 130 and/or the lateral surface135 w of the gate structure 130. In another embodiment, at least oneportion of the spacer 135 may be omitted. Under such design, thedielectric layer 150 may be formed on the sidewall 130 w of the ONOstructure 130 and the sidewall 134 w of the gate 134. In addition, thedielectric layer 150 has a thickness ranging between 500 angstrom and2000 angstrom.

The layer structure 160 covers the stop layer 150. The layer structure160 is, for example, an interlayer dielectric layer (ILD). The layerstructure 160 has a first opening 160 a 1, a second opening 160 a 2 andat least one third opening 160 a 3,

The first opening 160 a 1 passes through the layer structure 160 and thestop layer 140 and is filled with the first contact 172, such that thefirst contact 172 connects to the first doped region 122 through thefirst opening 160 a 1.

The second opening 160 a 2 passes through the layer structure 160 andthe stop layer 140 and is filled with the second contact 174, such thatthe second contact 174 connects to the second doped region 124 throughthe second opening 160 a 2.

The third openings 160 a 3 passing through the layer structure 160 andthe stop layer 140 is filled with the conductive portion 180, such thatthe conductive portions 180 connect to the dielectric layer 150 throughthe third openings 160 a 3. In another embodiment, the third openings160 a 3 may not pass through the stop layer 140, such that theconductive portions 180 connect to the dielectric layer 150 through thethird openings 160 a 3.

The first contact 172, the second contact 174 and the conductive portion180 may be formed in the same process, and accordingly the conductiveportion 180 made of material may be the same as the first contact 172and the second contact 174. The first contact 172, the second contact174 and the conductive portion 180 may be made of metal.

As shown in FIG. 1, a first curve C1 represents a relationship betweenthe position and the strength of electric field in the electroniccomponent 100, and a second curve 02 represents a relationship betweenthe position and the strength of electric field in a conventionalelectronic component without the dielectric layer 150 and the conductiveportions 180. The integral area A1 of the first curve C1 is larger thanthe integral area A2 of the second curve C2, and accordingly theelectronic component 100 may endure higher voltage than the conventionalelectronic component does.

FIG. 2 illustrates a top view of the electronic component 100 of FIG. 1.The number of the conductive portions 180 is plural and each conductiveportion 180 extends in a stripe along the upper surface 110 u. Inanother embodiment, the number of the conductive portions 180 may besingle.

FIG. 3 illustrates a top view of the electronic component 100 of FIG. 1according another embodiment. The number of the conductive portion 180may be single and extends in a polygon along the upper surface 110 u. Inanother embodiment, the number of the conductive portions 180 of FIG. 3may be plural.

In other embodiment, the number of the conductive portions 180 may besingle or plural, and at least one the conductive portions 180 extendsin a curve, a straight line or combination thereof along the uppersurface 110 u.

FIGS. 4A to 4F illustrate manufacturing processes of the electroniccomponent 100 of FIG. 1.

Referring to FIG. 4A, a dielectric layer material 150 covering the gatestructure 130 is formed on the upper surface 110 u of the semiconductorsubstrate 110.

The gate structure 130 includes a dielectric layer 130′, a gate 134 anda spacer 135. The gate 134 is formed on the dielectric layer 130′. Thespacer 135 is formed on the sidewall 130 w of the ONO structure 130 andthe sidewall 134 w of the gate 134. In another embodiment, the gatestructure 130 may have other structure different from that of the gatestructure 130 of FIG. 4A.

Referring to FIG. 4B, a portion of the dielectric layer material 150′ ofFIG. 4A is removed, and another portion of the dielectric layer material150′ is retained to form the dielectric layer 150. The dielectric layer150 covers at least one portion of the upper surface 130 u of the gatestructure 130, at least one portion of the lateral surface 135 w of thegate structure 130 and the upper surface 110 u of the semiconductorsubstrate 110. The dielectric layer 150 is a blockage film that definesthe regions of the first doped region 122 and the second doped region124.

Referring to FIG. 4C, the first doped region 122 and the second dopedregion 124 are formed on the semiconductor substrate 110, wherein thefirst doped region 122 and the second doped region 124 are embedded inthe semiconductor substrate 110.

Referring to FIG. 4D, the stop layer 140 covering the upper surface 110u, the first isolation portion 112, the second isolation portion 114,the first doped region 122, the second doped region 124, the gatestructure 130 and dielectric layer 150 is formed.

Referring to FIG. 4E, the layer structure 160 covering the stop layer160 is formed. In an embodiment, the layer structure 160 is aninterlayer dielectric layer, for example.

Referring to FIG. 4F, the first opening 160 a 1, the second opening 160a 2 and the third openings 160 a 3 passing through the layer structure160 and the stop layer 150 are formed.

Then, the first opening 160 a 1 is filled with the first contact 172 ofFIG. 1, the second opening 160 a 2 is filled with the second contact 174of FIG. 1 and the third openings 160 a 3 are filled with the conductiveportions 180 of FIG. 1 in the same process to form the electroniccomponent 100 of FIG. 1. The first contact 172, the second contact andthe conductive portions 180 are made of the same material, such asmetal.

While the invention has been described in terms of what is presentlyconsidered to be the most practical and preferred embodiments, it is tobe understood that the invention needs not be limited to the disclosedembodiment. On the contrary, it is intended to cover variousmodifications and similar arrangements included within the spirit andscope of the appended claims which are to be accorded with the broadestinterpretation so as to encompass all such modifications and similarstructures.

What is claimed is:
 1. An electronic component, comprising: asemiconductor substrate having an upper surface; a first doped regionembedded in the semiconductor substrate; a second doped region embeddedin the semiconductor substrate; a gate structure formed on the uppersurface; a dielectric layer formed above the upper surface and locatedbetween the first doped region and the second doped region; and aconductive portion formed on the dielectric layer.
 2. The electroniccomponent as claimed in claim 1, further comprises: a first contactconnecting to the first doped region; and a second contact connecting tothe second doped region; wherein the conductive portion made of materialis the same as that of the first contact and the second contact.
 3. Theelectronic component as claimed in claim 1, wherein the gate structurehas an upper surface and a lateral surface, and the dielectric layercovers the upper surface and the lateral surface of the gate structure.4. The electronic component as claimed in claim I. further comprises: astop layer; wherein the dielectric layer is formed between the uppersurface of the semiconductor substrate and the stop layer.
 5. Theelectronic component as claimed in claim 1, wherein the conductiveportion extends in a stripe along the upper surface.
 6. The electroniccomponent as claimed in claim , wherein the conductive portion extendsin a polygon along the upper surface.
 7. The electronic component asclaimed in claim 1, wherein the conductive portion extends in a curve, astraight line or combination thereof.
 8. An electronic component,comprising: a semiconductor substrate having an upper surface; a firstdoped region embedded in the semiconductor substrate; a second dopedregion embedded in the semiconductor substrate; and a conductive portionformed on a dielectric layer and located between the first doped regionand the second doped region but not formed on any doped region betweenthe first doped region and the second doped region.
 9. The electroniccomponent as claimed in claim 8, further comprises: a first contactconnecting to the first doped region; and a second contact connecting tothe second doped region; wherein the conductive portion made of materialis the same as that of the first contact and the second contact.
 10. Theelectronic component as claimed in claim 8, wherein the gate structurehas an upper surface and a lateral surface, and the dielectric layercovers the upper surface and the lateral surface of the gate structure.11. The electronic component as claimed in claim 8, further comprises: astop layer; wherein the dielectric layer is formed between the uppersurface of the semiconductor substrate and the stop layer.
 12. Theelectronic component as claimed in claim 8, wherein the conductiveportion extends in a stripe along the upper surface.
 13. The electroniccomponent as claimed in claim 8, wherein the conductive portion extendsin a polygon along the upper surface.
 14. The electronic component asclaimed in claim 8, wherein the conductive portion extends in a curve, astraight line or combination thereof.
 15. A manufacturing method of anelectronic component, comprising: forming a dielectric layer materialabove an upper surface of a semiconductor substrate, wherein thedielectric layer material covers a gate structure formed on the uppersurface; removing a portion of the dielectric layer material, whereinanother portion of the dielectric layer material is retained to form adielectric layer, and the dielectric layer formed above the uppersurface is located between the first doped region and the second dopedregion; forming a first doped region and a second doped region embeddedin the semiconductor substrate; and forming a conductive portion on thedielectric layer.
 16. The manufacturing method as claimed in claim 15,further comprises: forming a stop layer covering the first doped region,the second doped region, the gate structure and the dielectric layer;forming a layer structure covering the stop layer; forming a firstopening passing through the layer structure and the stop layer o exposethe first doped region; forming a second opening passing through thelayer structure and the stop layer to expose the second doped region;forming a third opening passing through the layer structure and the stoplayer to expose the conductive portion; and in the same process, fillingthe first opening with the first contact, filling the second openingwith the second contact, and filling the third opening with theconductive portion.
 17. The manufacturing method as claimed in claim 15,wherein in the step of removing the portion of the dielectric layermaterial, the gate structure has an upper surface and a lateral surface,and the dielectric layer covers the upper surface and the lateralsurface of the gate structure.
 18. The manufacturing method as claimedin claim 15, wherein in the step of forming the conductive portion onthe dielectric layer, the conductive portion extends in a curve, astraight line or combination thereof along the upper surface of thesemiconductor substrate.
 19. A manufacturing method of an electroniccomponent, comprising: forming a dielectric layer material above anupper surface of a semiconductor substrate, wherein the dielectric layermaterial covers a gate structure formed on the upper surface; removing aportion of the dielectric layer material, wherein another portion of thedielectric layer material is retained to form a dielectric layer, andthe dielectric layer formed above the upper surface is located betweenthe first doped region and the second doped region; forming a firstdoped region and a second doped region embedded in the semiconductorsubstrate; and forming a conductive portion on the dielectric layer,wherein the conductive portion is located between the first doped regionand the second doped region but not formed on any doped region betweenthe first doped region and the second doped region.
 20. Themanufacturing method as claimed in claim 19, further comprises: forminga stop layer covering the first doped region, the second doped region,the gate structure and the dielectric layer; forming a layer structurecovering the stop layer; forming a first opening passing through thelayer structure and the stop layer to expose the first doped region;forming a second opening passing through the layer structure and thestop layer to expose the second doped region; forming a third openingpassing through the layer structure and the stop layer to expose theconductive portion; and in the same process, filling the first openingwith the first contact, filling the second opening with the secondcontact, and filling the third opening with the conductive portion. 21.The manufacturing method as claimed in claim 19, wherein in the step ofremoving the portion of the dielectric layer material, the gatestructure has an upper surface and a lateral surface, and the dielectriclayer covers the upper surface and the lateral surface of the gatestructure.
 22. The manufacturing method as claimed in claim 19, whereinin the step of forming the conductive portion on the dielectric layer,the conductive portion extends in a curve, a straight line orcombination thereof along the upper surface of the semiconductorsubstrate.